April 14 - 17, 2019
San Francisco, California, USA

Accepted Papers

  1 Nikolay Ryzhenko, Steven Burns, Anton Sorokin and Mikhail Talalay Pin Access-Driven Design Rule Clean and DFM Optimized Routing of Standard Cells under Boolean Constraints
  2 Gyuszi Suto, Geoff Greenleaf, Sanjay Soni, Heinrich Fischer, Phanindra Bhagavatula, Renato Hentschke and Brian Miller Declarative Language for Geometric Pattern Matching in VLSI Process Rule Modeling
  3 Ankur Sharma, David Chinnery and Chris Chu Lagrangian Relaxation Based Gate Sizing with Clock Skew Scheduling - A Fast and Effective Approach
  4 Alexandre Truppel, Tsun-Ming Tseng, Davide Bertozzi, José Alves and Ulf Schlichtmann PSION: Combining Logical Topology and Physical Layout Optimization for Wavelength-Routed ONoCs
  5 Xiao Shi, Hao Yan, Jinxin Wang, Xiaofen Xu, Fengyuan Liu, Longxing Shi and Lei He Adaptive Clustering and Sampling for High-Dimensional and Multi-Failure-Region SRAM Yield Analysis
  6 Sheng-En David Lin and Dae Hyun Kim Construction of All Multilayer Monolithic Rectilinear Steiner Minimum Trees on the 3D Hanan Grid for Monolithic 3D IC Routing
  7 Xingquan Li, Jianli Chen, Wenxing Zhu and Yao-Wen Chang Analytical Mixed-Cell-Height Legalization Considering Average and Maximum Movement Minimization
  8 Biying Xu, Shaolan Li, Chak-Wa Pui, Derong Liu, Linxiao Shen, Yibo Lin, Nan Sun and David Pan Device Layer-Aware Analytical Placement for Analog Circuits
  9 Dongwon Park, Ilgweon Kang, Yeseong Kim, Sicun Gao, Bill Lin and Chung-Kuan Cheng RODE: Efficient Routability Diagnosis and Estimation Framework Based on SAT Techniques
  10 Ya-Chu Chang, Tung-Wei Lin, Iris Hui-Ru Jiang and Gi-Joon Nam Graceful Register Clustering by Effective Mean Shift Algorithm for Balancing Power and Timing
  11 Renan Netto, Sheiny Fabre, Tiago Augusto Fontana, Vinicius Livramento, Laércio Pilla and Jose Luís Güntzel How Deep Learning Can Drive Physical Synthesis Towards more Predictable Legalization
  12 Hua-Yu Chang and Iris Hui-Ru Jiang Multiple Patterning Layout Compliance with Minimizing Topology Disturbance and Polygon Displacement